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19-3035; Rev 1; 11/03
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
General Description
The MAX5065/MAX5067 dual-phase, PWM controllers provide high-output-current capability in a compact package with a minimum number of external components. The MAX5065/MAX5067 utilize a dual-phase, average-current-mode control that enables optimal use of low RDS(ON) MOSFETs, eliminating the need for external heatsinks even when delivering high output currents. Differential sensing enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. An internal regulator enables operation with input voltage ranges of +4.75V to +5.5V or +8V to +28V. The high switching frequency, up to 500kHz per phase, and dual-phase operation allow the use of low-output inductor values and input capacitor values. This accommodates the use of PC boardembedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, and low system cost. The MAX5065/MAX5067 also feature a clock input (CLKIN) for synchronization to an external clock, and a clock output (CLKOUT) with programmable phase delay (relative to CLKIN) for paralleling multiple phases. The MAX5065/MAX5067 also limit the reverse current if the bus voltage becomes higher than the regulated output voltage. These devices are specifically designed to limit current sinking when multiple power-supply modules are paralleled. The MAX5065 offers an adjustable +0.6V to +3.3V output voltage. The MAX5067 output voltage is adjustable from +0.8V to +3.3V and features an overvoltage protection and a power-good output signal. The MAX5065/MAX5067 operate over the extended temperature range (-40C to +85C). The MAX5065 is available in a 28-pin SSOP package. The MAX5067 is available in a 44-pin thin QFN package. Refer to the MAX5037A data sheet for a VRM 9.0/VRM 9.1-compatible, VID-controlled output voltage controller in a 44-pin QFN package.
Features
o +4.75V to +5.5V or +8V to +28V Input Voltage Range o Adjustable VOUT +0.6V to +3.3V (MAX5065) +0.8V to +3.3V (MAX5067) o Up to 60A Output Current o Internal Voltage Regulator for a +12V or +24V Power Bus o Programmable Adaptive Output Voltage Positioning o True Differential Remote Output Sensing o Out-of-Phase Controllers Reduce Input Capacitance Requirement and Distribute Power Dissipation o Average-Current-Mode Control Superior Current Sharing Between Individual Phases and Paralleled Modules Accurate Current Limit Eliminates MOSFET and Inductor Derating o Limits Reverse-Current Sinking in Paralleled Modules o Integrated 4A Gate Drivers o Selectable Fixed Frequency 250kHz or 500kHz Per Phase (Up to 1MHz for Two Phases) o External Frequency Synchronization from 125kHz to 600kHz o Internal PLL with Clock Output for Paralleling Multiple DC-DC Converters o Thermal Protection o 28-Pin SSOP Package (MAX5065) o 44-Pin Thin QFN Package (MAX5067)
MAX5065/MAX5067
Applications
Servers and Workstations Point-of-Load High-Current/High-Density Telecom DC-DC Regulators Networking Systems Large-Memory Arrays RAID Systems High-End Desktop Computers
Ordering Information
PART MAX5065EAI MAX5067ETH TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 SSOP 44 Thin QFN
Selector Guide and Pin Configurations appear at end of data sheet.
________________________________________________________________Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
ABSOLUTE MAXIMUM RATINGS
IN to SGND.............................................................-0.3V to +30V BST_ to SGND ........................................................-0.3V to +35V DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V] DL_ to PGND ..............................................-0.3V to (VCC + 0.3V) BST_ to LX_ ..............................................................-0.3V to +6V VCC to SGND............................................................-0.3V to +6V VCC, VDD to PGND ...................................................-0.3V to +6V SGND to PGND .....................................................-0.3V to +0.3V All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derate 9.5mW/C above +70C) ............762mW 44-Pin Thin QFN (derate 27.0mW/C above+70C) ...2162mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER SYSTEM SPECIFICATIONS 8 Input Voltage Range Quiescent Supply Current Efficiency OUTPUT VOLTAGE No load SENSE+ to SENSE- Accuracy (Note 4) MAX5065 No load, VCC = +4.75V to +5.5V or VIN = +8V to +28V No load MAX5067 No load, VCC = +4.75V to +5.5V or VIN = +8V to +28V STARTUP/INTERNAL REGULATOR VCC Undervoltage Lockout VCC Undervoltage Lockout Hysteresis VCC Output Accuracy MOSFET DRIVERS Output Driver Impedance Output Driver Source/Sink Current Nonoverlap Time OSCILLATOR AND PLL Switching Frequency PLL Lock Range PLL Locking Time fSW fPLL tPLL CLKIN = SGND CLKIN = VCC 238 475 125 200 250 500 262 525 600 kHz kHz s RON IDH_, IDL_ tNO CDH_/DL_ = 5nF Low or high output 1 4 60 3 A ns VIN = +8V to +28V, ISOURCE = 0 to 80mA 4.85 UVLO VCC rising 4.0 4.15 200 5.1 5.30 4.5 V mV V 0.5952 0.594 0.7936 0.792 0.6 0.6 0.8 0.8 0.6048 0.6064 0.8064 0.808 V VIN IQ Short IN and VCC together for +5V input operation EN = VCC or SGND ILOAD = 52A (26A per phase) 4.75 4 90 28 5.50 10 V mA % SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER CLKOUT Phase Shift (At fSW = 125kHz) CLKIN Input Pulldown Current CLKIN High Threshold CLKIN Low Threshold CLKIN High Pulse Width PHASE High Threshold PHASE Low Threshold PHASE Input Bias Current CLKOUT Output Low Level CLKOUT Output High Level CURRENT LIMIT Average Current-Limit Threshold Reverse Current-Limit Threshold Cycle-by-Cycle Current Limit Cycle-by-Cycle Overload Response Time CURRENT-SENSE AMPLIFIER CSP_ to CSN_ Input Resistance Common-Mode Range Input Offset Voltage Amplifier Gain 3dB Bandwidth Transconductance Open-Loop Gain Common-Mode Voltage Range DIFF Output Voltage Input Offset Voltage Amplifier Gain 3dB Bandwidth Minimum Output Current Drive SENSE+ to SENSE- Input Resistance RCS_ VCMR(CS) VOS(CS) AV(CS) f3dB gmca AVOL(CE) VCMR(DIFF) VCM VOS(DIFF) AV(DIFF) f3dB IOUT(DIFF) RVS_ CDIFF = 20pF 1.0 50 100 VSENSE+ = VSENSE- = 0 -1 0.997 1 3 No load -0.3 0.6 +1 1.003 -0.3 -1 18 4 550 50 +1.0 4 +3.6 +1 k V mV V/V MHz S dB V V mV V/V MHz mA k VCL VCLR VCLPK tR CSP_ to CSN_ CSP_ to CSN_ CSP_ to CSN_ (Note 3) VCSP_ to VCSN_ = +150mV 45 -3.9 90 112 260 48 51 -0.2 130 mV mV mV ns SYMBOL PHASE = VCC CONDITIONS PHASE = unconnected PHASE = SGND ICLKIN VCLKINH VCLKINL tCLKIN VPHASEH VPHASEL IPHASEBIAS VCLKOUTL ISINK = 2mA (Note 2) 4.5 VCLKOUTH ISOURCE = 2mA (Note 2) -50 200 4 1 +50 100 MIN 115 85 55 3 2.4 0.8 TYP 120 90 60 5 MAX 125 95 65 7 A V V ns V V A mV V degrees UNITS
MAX5065/MAX5067
CLKOUT
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical specifications are at TA = +25C.) (Note 1)
PARAMETER Open-Loop Gain Unity-Gain Bandwidth EAN Input Bias Current Error-Amplifier Output Clamping Voltage SYMBOL AVOL(EA) fUGEA IB(EA) VEAN = +2.0V -100 810 CONDITIONS MIN TYP 70 3 +100 918 MAX UNITS dB MHz nA mV
VOLTAGE-ERROR AMPLIFIER (EAOUT)
VCLAMP(EA) With respect to VCM
POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN VOV PGOOD Trip Level (MAX5067) VUV PGOOD Output Low Level (MAX5067) PGOOD Output Leakage Current (MAX5067) Phase Failure Trip Threshold (MAX5067) OVPIN Trip Threshold (MAX5067) OVPIN Input Resistance (MAX5067) THERMAL SHUTDOWN Thermal Shutdown Thermal-Shutdown Hysteresis EN INPUT EN Input Low Voltage EN Input High Voltage EN Pullup Current VENL VENH IEN 3 4.5 5 5.5 1 V V A TSHDN 150 8 C C VPGLO IPG VPH OVPTH ROVPIN PGOOD goes low when VOUT is outside this window ISINK = 4mA PGOOD = VCC PGOOD goes low when CLP_ is higher than VPH With respect to SGND 0.792 190 2 0.8 280 0.808 370 -12.5 -10 -8.5 0.2 1 V A V V k PGOOD goes low when VOUT is outside this window +6 +8 +10 %VOUT
Note 1: Note 2: Note 3: Note 4:
Specifications from -40C to 0C are guaranteed by characterization but not production tested. Guaranteed by design. Not production tested. See Peak-Current Comparator section. Does not include an error due to finite error amplifier gain. See the Voltage-Error Amplifier section.
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Typical Operating Characteristics
(Circuit of Figure 1. TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE
MAX5065/67 toc02
MAX5065/MAX5067
EFFICIENCY vs. OUTPUT CURRENT AND INTERNAL OSCILLATOR FREQUENCY
MAX5065/67 toc01
EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE
100 90 80 70 VIN = +12V VIN = +5V (%) 100 90 80 70 60 50 40 30 20 VOUT = +1.8V fSW = 250kHz 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) 10 0
90 80 (%) 70 60 50 40
f = 500kHz f = 250kHz
VIN = +12V VIN = +5V
(%)
60 50 40 30 20
VIN = +5V VOUT = +1.8V 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A)
10 0
VOUT = 1V fSW = 250kHz 0 4 8 12 16 20 24 28 32 36 40 44 48 52 OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
MAX5065/67 toc04
EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE
MAX5065/67 toc05
EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE
90 80 70 (%) 60 50 40 30 20 VOUT = +1V VOUT = +1.5V VOUT = +1.8V
MAX5065/67 toc06
100 90 80 70 (%)
100 90 80 70 (%) 60 50 40 30 VOUT = +1V VOUT = +1.5V VOUT = +1.8V
100
60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) VIN = +24V VOUT = +1.8V fSW = 125kHz
20 10 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 OUTPUT CURRENT (A) VIN = +12V fSW = 250kHz
10 0
VIN = +12V fSW = 500kHz 0 4 8 12 16 20 24 28 32 36 40 44 48 52 OUTPUT CURRENT (A)
SUPPLY CURRENT vs. FREQUENCY AND INPUT VOLTAGE
MAX5065/67 toc07
SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY
MAX5065/67 toc08
SUPPLY CURRENT vs. LOAD CAPACITANCE PER DRIVER
90 80 70 ICC (mA) 60 50 40 30
MAX5065/67 toc09
12.0 11.5 11.0 10.5 ICC (mA) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 VIN = +5V EXTERNALCLOCK NO DRIVER LOAD VIN = +12V VIN = +24V
100 90 80 70 ICC (mA) 60 50 40 30 20 10 0 VIN = +12V CDL_ = 22nF CDH_ = 8.2nF -40 -15 10 35 60 125kHz 250kHz
100
20 10 0 85 1 3 5 7 9 11 13 15 CDRIVER (nF) VIN = +12V fSW = 250kHz
100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (kHz)
TEMPERATURE (C)
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MAX5065/67 toc03
100
5
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD vs. OUTPUT VOLTAGE
54 53 (VCSP_ - VCSN_) (mV) 52 VOV (V) 51 50 49 48 47 46 45 1.0 1.1 1.2 1.3 1.4 VOUT (V) 1.5 1.6 1.7 1.8 0.1 4.7 PHASE 2 PHASE 1
MAX5065/67 toc10
OVERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE
MAX5065/67 toc11
UNDERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE
MAX5065/67 toc12
55
10
10
VOUT = +3.3V VUV (V)
VOUT = +3.3V 1 VOUT = +0.8V
1 VOUT = +0.8V
0.1 4.8 4.9 5.0 5.1 VIN (V) 5.2 5.3 5.4 5.5 4.7 4.8 4.9 5.0 5.1 VIN (V) 5.2 5.3 5.4 5.5
OUTPUT VOLTAGE vs. OUTPUT CURRENT AND ERROR AMP GAIN (RF/RIN)
MAX5065/67 toc13
DIFFERENTIAL AMPLIFIER BANDWIDTH
3.5 3.0 PHASE 2.5 GAIN (V/V) 2.0 -90 1.5 1.0 GAIN -135 -180 -225 -270 0.01 0.1 1 10 FREQUENCY (MHz)
MAX5065/67 toc14
DIFF OUTPUT ERROR vs. SENSE+ TO SENSE- VOLTAGE
45 0 PHASE (deg) ERROR (%) -45 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VSENSE (V) VIN = +12V NO DRIVER
MAX5065/67 toc15
1.90 1.85 1.80 1.75 VOUT (V) 1.70 1.65 1.60 1.55 1.50 RF/RIN = 10 RF/RIN = 7.5 RF/RIN = 40
90
0.200
RF/RIN = 20
0.5 0
0 4 8 12 16 20 24 28 32 36 40 44 48 52 ILOAD (A)
VCC LOAD REGULATION vs. INPUT VOLTAGE
MAX5065/67 toc16
VCC LINE REGULATION
MAX5065/67 toc17
VCC LINE REGULATION
5.20 5.15 5.10
MAX5065/67 toc18
5.20 5.15 5.10 5.05 VCC (V) VIN = +24V VIN = +12V
5.25 5.20 5.15 5.10 VCC (V) ICC = 0 ICC = 40mA
5.25
5.00 4.95 4.90 4.85 DC LOAD 4.80 0
VIN = +8V
5.00 4.95 4.90 4.85 4.80 4.75 8 10 12 14 16 18 20 22 24 26 28 VIN (V)
VCC (V)
5.05
5.05 5.00 4.95 4.90 4.85 4.80 4.75 8 ICC = 80mA 9 10 11 VIN (V) 12 13
15 30 45 60 75 90 105 120 135 150 ICC (mA)
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
DRIVER RISE TIME vs. DRIVER LOAD CAPACITANCE
MAX5065/67 toc19
MAX5065/MAX5067
DRIVER FALL TIME vs. DRIVER LOAD CAPACITANCE
MAX5065/67 toc20
HIGH-SIDE DRIVER (DH_) SINK AND SOURCE CURRENT
MAX5065/67 toc21
120 110 100 90 80 tR (ns) 70 60 50 40 30 20 10 0 1 6 11 16 21 CDRIVER (nF)
120 110 100 90 80 tR (ns) 70 60 50 40 30 20 10 0 1 6 11 16 21 CDRIVER (nF)
DL_ DH_
DL_ DH_
DH_ 1.6A/div
VIN = +12V fSW = 250kHz 26 31 36
VIN = +12V fSW = 250kHz 26 31 36
VIN = +12V CDH_ = 22nF 100ns/div
LOW-SIDE DRIVER (DL_) SINK AND SOURCE CURRENT
MAX5065/67 toc22
PLL LOCKING TIME 250kHz TO 350kHz AND 350kHz TO 250kHz MAX5065/67 toc23
CLKOUT 5V/div 350kHz DL_ 1.6A/div PLLCMP 200mV/div 250kHz 0
VIN = +12V CDL_ = 22nF 100ns/div
VIN = +12V NO LOAD 100s/div
PLL LOCKING TIME 250kHz TO 500kHz AND 500kHz TO 250kHz MAX5065/67 toc24
CLKOUT 5V/div CLKOUT 5V/div
PLL LOCKING TIME 250kHz TO 150kHz AND 150kHz TO 250kHz MAX5065/67 toc25
250kHz 500kHz PLLCMP 200mV/div 250kHz 0 100s/div VIN = +12V NO LOAD PLLCMP 200mV/div 150kHz 0 VIN = +12V NO LOAD 100s/div
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
HIGH-SIDE DRIVER (DH_) RISE TIME
MAX5065/67 toc26
HIGH-SIDE DRIVER (DH_) FALL TIME
MAX5065/67 toc27
DH_ 2V/div
DH_ 2V/div
VIN = +12V CDH_ = 22nF 40ns/div
VIN = +12V CDH_ = 22nF 40ns/div
LOW-SIDE DRIVER (DL_) RISE TIME
MAX5065/67 toc28
LOW-SIDE DRIVER (DL_) FALL TIME
MAX5065/67 toc29
DL_ 2V/div
DL_ 2V/div
VIN = +12V CDL_ = 22nF 40ns/div
VIN = +12V CDL_ = 22nF 40ns/div
OUTPUT RIPPLE
MAX5065/67 toc30
INPUT STARTUP RESPONSE
MAX5065/67 toc31
VPGOOD 1V/div
VOUT (AC-COUPLED) 10mV/div
VOUT 1V/div
VIN 5V/div VIN = +12V VOUT = +1.75V IOUT = 52A 500ns/div 2ms/div VIN = +12V VOUT = +1.75V IOUT = 52A
8
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C, unless otherwise noted.)
REVERSE CURRENT SINK vs. TEMPERATURE
MAX5065/67 toc34
MAX5065/MAX5067
ENABLE STARTUP RESPONSE
MAX5065/67 toc32
LOAD-TRANSIENT RESPONSE
MAX5065/67 toc33
2.8
VPGOOD 1V/div
2.7 VEXTERNAL = +3.3V IREVERSE (A) VOUT 50mV/div 2.6
VOUT 1V/div
2.5 VEXTERNAL = +2V 2.4 VIN = +12V VOUT = 1.5V 2.3 R1 = R2 = 1.5m 10 35 60 85
VIN = +12V VOUT = +1.75V IOUT = 52A 1ms/div
VEN 2V/div
VIN = +12V VOUT = +1.75V ISTEP = 8A TO 52A tRISE = 1s 40s/div
-40
-15
TEMPERATURE (C)
REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V)
MAX5065/67 toc35
REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5065/67 toc36
REVERSE CURRENT 5A/div 0A
REVERSE CURRENT 10A/div 0A
R1 = R2 = 1.5m 200s/div
R1 = R2 = 1.5m 200s/div
REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V)
MAX5065/67 toc37
REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5065/67 toc38
REVERSE CURRENT 5A/div 0A
REVERSE CURRENT 10A/div 0A
R1 = R2 = 1.5m 200s/div
R1 = R2 = 1.5m 200s/div
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Pin Description
PIN MAX5065 1, 13 MAX5067 39, 16 NAME CSP2, CSP1 CSN2, CSN1 PHASE FUNCTION Current-Sense Differential Amplifier Positive Inputs. Sense the inductor current. The differential voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18. Current-Sense Differential Amplifier Negative Inputs. Together with CSP_, sense the inductor current. Phase-Shift Setting Input. Connect PHASE to VCC for 120, leave PHASE unconnected for 90, or connect PHASE to SGND for 60 of phase shift between the rising edge of CLKOUT and CLKIN/DH1. External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see the Phase-Locked Loop section). Current-Error Amplifier Outputs. Compensate the current loop by connecting an RC network to ground. Signal Ground. Ground connection for the internal control circuitry. Differential Output-Voltage-Sensing Positive Input. Used to sense a remote load. The MAX5065 and MAX5067 regulate the difference between SENSE+ and SENSE- according to the factory preset reference voltage of +0.6V and +0.8V, respectively. Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to VOUT- or PGND at the load. Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier. Voltage-Error Amplifier Inverting Input. Receives a signal from the output of the differential remote-sense amplifier. Referenced to SGND. Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error amplifier gain-setting resistors determine the amount of adaptive voltage positioning. Output Enable. A logic-low shuts down the power drivers. EN has an internal 5A pullup current. Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply. Connect a 0.47F ceramic capacitor between BST_ and LX_. High-Side Gate-Driver Outputs. Drive the gate of the high-side MOSFET. Inductor Connection. Source connection for the high-side MOSFETs. Also serve as the return terminal for the high-side driver.
2, 14
40, 17
3
41
4 5, 7 6 8
42 43, 7 5, 20, 35 10
PLLCMP CLP2, CLP1 SGND SENSE+
9 10 11
11 12 13
SENSEDIFF EAN
12
14
EAOUT
15 16, 26 17, 25 18, 24 19, 23 20
19 22, 34 23, 32 24, 31 25, 30 27
EN BST1, BST2 DH1, DH2 LX1, LX2
DL1, DL2 Low-Side Gate-Driver Outputs. Synchronous MOSFET gate drivers for the two phases. VCC Internal +5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7F and 0.1F ceramic capacitors in parallel. Supply Voltage Connection. Connect IN to VCC for a +5V system. Connect the unregulated power source to IN through an RC lowpass filter comprised of a 2.2 resistor and a 0.1F ceramic capacitor. Power Ground. Connect the VCC bypass capacitors, input capacitors, output capacitors, and low-side synchronous MOSFET source to PGND.
21
28
IN
22
29
PGND
10
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Pin Description (continued)
PIN MAX5065 27 MAX5067 36 NAME CLKOUT FUNCTION Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount determined by the PHASE input. Use CLKOUT to parallel additional MAX5065/MAX5067s. CMOS Logic Clock Input. Drive CLKIN with a frequency range between 125kHz and 600kHz or connect to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5A pulldown current. Overvoltage Protection Circuit Input. Connect OVPIN to the center of the resistive-divider between VOUT and GND. When OVPIN exceeds +0.8V with respect to SGND, OVPOUT latches DH_ low and DL_ high. Toggle EN low to high or recycle the power to reset the latch. Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a safety device such as an SCR. Power-Good Output. The open-drain, active-low PGOOD output goes low when the output voltage falls out of regulation or a phase failure is detected. The power-good windowcomparator thresholds are +8% and -10% of the output voltage. Forcing EN low also forces PGOOD low.
MAX5065/MAX5067
28
38
CLKIN
--
6
OVPIN
--
8
OVPOUT
--
9
PGOOD
--
1, 2, 3, 4, 15, 18, 21, 33, 37, 44 26
N.C.
No Connection. Not internally connected. Supply Voltage for Low-Side and High-Side Drivers. VCC powers VDD. Connect a parallel combination of 0.1F and 1F ceramic capacitors to PGND and a 1 resistor to VCC to filter out the high peak currents of the driver from the internal circuitry.
--
VDD
Detailed Description
The MAX5065/MAX5067 average-current-mode PWM controllers drive two out-of-phase buck converter channels. Average-current-mode control improves current sharing between the channels while minimizing component derating and size. Parallel multiple MAX5065/ MAX5067 regulators to increase the output current capacity. For maximum ripple rejection at the input, set the phase shift between phases to 90 for two paralleled converters, or 60 for three paralleled converters. Paralleling the MAX5065/MAX5067s improves design flexibility in applications requiring upgrades (higher load). Dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the MAX5065/MAX5067 consists of an inner average current loop controlled by a common outer-loop voltageerror amplifier (VEA). The combined action of the two inner current loops and the outer voltage loop corrects the output voltage errors and forces the phase currents to be equal. Program the output voltage from +0.6V to
+3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) using a resistive-divider at SENSE+ and SENSE-.
VIN, VCC, VDD The MAX5065/MAX5067 accept a wide input voltage range of +4.75V to +5.5V or +8V to +28V. All internal control circuitry operates from an internally regulated nominal voltage of +5V (VCC). For input voltages of +8V or greater, the internal VCC regulator steps the voltage down to +5V. The VCC output voltage regulates to +5V while sourcing up to 80mA. Bypass VCC to SGND with 4.7F and 0.1F low-ESR ceramic capacitors for highfrequency noise rejection and stable operation (Figures 1, 2, and 3). Calculate power dissipation in the MAX5065/MAX5067 as a product of the input voltage and the total VCC regulator output current (ICC). ICC includes quiescent current (IQ) and gate-drive current (IDD): (1) PD = VIN x ICC
ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4) (2)
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11
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Functional Diagrams
EN
IN
+5V LDO REGULATOR
UVLO POR TEMP SENSOR TO INTERNAL CIRCUITS
VCC
CSP1 CSN1 CLP1 SGND
TO INTERNAL CIRCUITS
CSP1 CSN1 CLP1 CLK
DRV_VCC
SHDN
BST1 DH1
PHASE 1
LX1 DL1
MAX5065
GMIN CLKIN PHASE CLKOUT PLLCMP DIFF SENSEDIFF AMP SENSE+ EAOUT EAN ERROR AMP DRV_VCC CLK VREF = 0.6V + VCM RAMP2 GMIN CLP2 CSN2 CSP2 CLP2 CSN2 CSP2 PHASE 2 PGND DH2 LX2 DL2 BST2 SHDN 0.6V RAMP GENERATOR PHASELOCKED LOOP PGND RAMP1
PGND
12
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Functional Diagrams (continued)
MAX5065/MAX5067
EN
IN
+5V LDO REGULATOR
UVLO POR TEMP SENSOR
VCC VDD TO INTERNAL CIRCUITS
CSP1 CSN1 CLP1 SGND
CSP1 CSN1 CLP1 CLK
DRV_VCC
SHDN
BST1 DH1
PHASE 1
LX1 DL1
MAX5067
GMIN CLKIN PHASE CLKOUT PLLCMP DIFF CLP2 SENSEDIFF AMP SENSE+ EAOUT EAN ERROR AMP DRV_VCC CLK VREF = 0.8V + VCM RAMP2 OVPIN CLP2 CSN2 CSP2 GMIN CLP2 CSN2 CSP2 PHASE 2 PGND DH2 LX2 DL2 BST2 SHDN 0.8V OVP COMP OVPOUT +0.6V VREF RAMP GENERATOR PHASELOCKED LOOP PGND RAMP1
CLP1 DIFF POWERGOOD GENERATOR
PGOOD
N PGND
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13
MAX5065/MAX5067
Figure 1. Typical Application Circuit, VIN = +5V
VIN = +5V VCC VCC C31 R13 IN C42 VIN EN C3-C7 Q1 L1 LX1 DL1 Q2 D1 C12 R1 PLLCMP CLKIN IN SENSE- SENSE+ CSN1 CSP1 DH1 C32 R4 C1, C2 BST1 IN RH C14 C15 C16 C25 LOAD RL C26, C30, C37 VOUT = +0.8V TO +3.3V AT 52A VCC C41 C38 OVPOUT R3 VDD C39 C40 D4 D3
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
14
MAX5067
OVPIN DIFF EAN EAOUT DL2 Q4 C13 D2 LX2 DH2 Q3 L2 R2 C8 C11 VIN CLP1 CLP2 PGND SGND PHASE PGOOD CSN2 CSP2 BST2 R6 C34 C35 C33 R5 VCC PGOOD R11
VIN
C43
R12
RA
RB
C44
RIN
Rf
RX
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VCC
C36
VIN = +8V TO +28V VCC VCC C31 R13 C32 R4 C42 VIN EN C3-C7 Q1 L1 LX1 DL1 Q2 D1 C12 R1 PLLCMP CLKIN IN SENSE- SENSE+ CSN1 CSP1 DH1 C1, C2
VIN
Figure 2. Typical VRM Application Circuit, VIN = +8V to +28V
OVPOUT R12 C41 C38 D4 C39 C40 R3 VDD C14, C15 C16- C25 LOAD RL C26- C30, C37 VCC BST1 D3 RH VOUT = +1.8V AT 52A OVPIN
C43
RA
MAX5067
RB RIN DIFF EAN DH2 LX2 DL2 Q4 C13 D2 Q3 L2 Rf EAOUT C8- C11 VIN
C44
VCC
RX
R2
CLP1
CLP2
PGND SGND PHASE PGOOD CSN2 CSP2
BST2
R6 C36 C34 C35 C33
R5 VCC PGOOD
R11
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
MAX5065/MAX5067
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NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
15
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
SENSESENSE+ 3 PHASE CSN1 CSP1 15 EN VIN = +12V C1, C2 R1 21 IN C39 DH1 LX1 VCC 28 DL1 CLKIN
9 8 14 13 VIN C3-C7 17 18 19 Q2 D1 C12
Q1 L1 R2
MAX5065
4 PLLCMP C25 C26 R4 BST1 16 VCC 20 C32 R7 10 11 C34 C31 RH DIFF EAN EAOUT DH2 25 LX2 24 Q1 L2 R3 VIN C8-C11 D4 C14, C15 C16-C24, LOAD C33 RL D3 +1.8V AT 60A VOUT
VCC RX
R8
12
C29 C30
R6
7
CLP1
DL2 23
Q2 D2
C13
C28 C27 R5
5
BST2 26 CLP2
6 22 SGND PGND CSP2 CSN2
1 2
Figure 3. MAX5065 Typical Application Circuit
16
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
where, Q G1, Q G2, Q G3, and Q G4 are the total gate charge of the low-side and high-side external MOSFETs, IQ is 4mA (typ), and fSW is the switching frequency of each individual phase. For applications utilizing a +5V input voltage, disable the VCC regulator by connecting IN and VCC together.
Control Loop
The MAX5065/MAX5067 use an average-current-mode control scheme to regulate the output voltage (Figure 4). The main control loop consists of an inner current loop and an outer voltage loop. The inner loop controls the output currents (IPHASE1 and IPHASE2) while the outer loop controls the output voltage. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a singlepole system. The current loop consists of a current-sense resistor (RS), a current-sense amplifier (CA_), a current-error amplifier (CEA_), an oscillator providing the carrier ramp, and a PWM comparator (CPWM_). The precision CA_ amplifies the sense voltage across RS by a factor of 18. The inverting input to the CEA_ senses the CA_ output. The CEA_ output is the difference between the voltage-error amplifier output (EAOUT) and the gainedup voltage from the CA_. The RC compensation network connected to CLP1 and CLP2 provides external frequency compensation for the respective CEA_. The start of every clock cycle enables the high-side drivers and initiates a PWM ON cycle. Comparator CPWM_ compares the output voltage from the CEA_ with a 0 to +2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage. The outer voltage control loop consists of the differential amplifier (DIFF AMP), reference voltage, and VEA. The unity-gain differential amplifier provides true differential remote sensing of the output voltage. The differential amplifier output connects to the inverting input (EAN) of the VEA. The noninverting input of the VEA is internally connected to an internal precision reference voltage. The MAX5067 reference voltage is set to +0.8V and the MAX5065 reference is set to +0.6V. The VEA controls the two inner current loops (Figure 4). Use a resistive feedback network to set the VEA gain as required by the adaptive voltage-positioning circuit (see the Adaptive Voltage Positioning section). Current-Sense Amplifier The differential current-sense amplifier (CA_) provides a DC gain of 18. The maximum input offset voltage of the current-sense amplifier is 1mV and the common-mode voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor. Peak-Current Comparator The peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 5). Note that the average current-limit threshold of 48mV still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output
17
MAX5065/MAX5067
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5065/MAX5067 include an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO threshold is internally set between +4.0V and +4.5V with a 200mV hysteresis. Hysteresis at UVLO eliminates "chattering" during startup. Most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4V. The MAX5065/MAX5067 draw up to 4mA of current before the input voltage reaches the UVLO threshold. The compensation network at the current-error amplifiers (CLP1 and CLP2) provides an inherent soft-start of the output voltage. It includes a parallel combination of capacitors (C34, C36) and resistors (R5, R6) in series with other capacitors (C33, C35) (see Figures 1 and 2). The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on CLP_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180 out-of-phase clock signals required by the pulse-width modulation (PWM) circuits. The oscillator also generates the 2VP-P voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator frequency to 250kHz or connect CLKIN to VCC to set the internal oscillator to 500kHz. CLKIN is a CMOS logic clock input for the phaselocked loop (PLL). When driven externally, the internal oscillator locks to the signal at CLKIN. A rising edge at CLKIN starts the ON cycle of the PWM. Ensure that the external clock pulse width is at least 200ns. CLKOUT provides a phase-shifted output with respect to the rising edge of the signal at CLKIN. PHASE sets the amount of phase shift at CLKOUT. Connect PHASE to VCC for 120 of phase shift, leave PHASE unconnected for 90 of phase shift, or connect PHASE to SGND for 60 of phase shift with respect to CLKIN. The MAX5065/MAX5067 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL to generate the proper clock signal required for PWM operation.
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
inductor with a saturation current specification greater than the average current limit (48mV). Proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a cracked output inductor. The 112mV voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. The peak-current comparator has a delay of only 260ns. up slope to the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section). PWM Comparator and R-S Flip-Flop The PWM comparator (CPWM) sets the duty cycle for each cycle by comparing the output of the current-error amplifier to a 2VP-P ramp. At the start of each clock cycle, an R-S flip-flop resets and the high-side driver (DH_) turns on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the CLP_ voltage, thus terminating the ON cycle (Figure 5). Differential Amplifier The differential amplifier (DIFF AMP) facilitates output voltage remote sensing at the load (Figure 4). It provides true differential output voltage sensing while rejecting the common-mode voltage errors due to highcurrent ground paths. Sensing the output voltage
Current-Error Amplifier
Each phase of the MAX5065/MAX5067 has a dedicated transconductance current-error amplifier (CEA_) with a typical gm of 550S and 320A output sink and source current capability. The current-error amplifier outputs, CLP1 and CLP2, serve as the inverting input to the PWM comparator. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (Figure 4). Compensate CEA_ so the inductor current down slope, which becomes the
RCF
CCF
CSN1
CSP1
CLP1
CCFF
MAX5065/ MAX5067
CA1
VIN
RF* SENSE+ DIFF AMP SENSERIN* VEA
CEA1 CPWM1
IPHASE1 DRIVE 1 RS
VOUT VIN CEA2 CPWM2 DRIVE 2 IPHASE2 COUT RS LOAD
VREF
CA2
CSN2
CSP2
CLP2
RCF
CCF
*RF AND RIN ARE EXTERNAL. CCCF
Figure 4. MAX5065/MAX5067 Control Loop 18 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
directly at the load provides accurate load voltage sensing in high-current environments. The VEA provides the difference between the differential amplifier output (DIFF) and the desired output voltage. The differential amplifier has a bandwidth of 3MHz. The difference between SENSE+ and SENSE- regulates to +0.6V for the MAX5065 and regulates to +0.8V for the MAX5067. Connect SENSE+ to the center of the resistive-divider from the output to SENSE-. Voltage-Error Amplifier The VEA sets the gain of the voltage control loop and determines the error between the differential amplifier output and the internal reference voltage (VREF). The VEA output clamps to +0.9V relative to V CM (+0.6V), thus limiting the average maximum current from individual phases. The maximum average currentlimit threshold for each phase is equal to the maximum clamp voltage of the VEA divided by the gain (18) of the current-sense amplifier. This results in accurate settings for the average maximum current for each phase. Set the VEA gain using RF and RIN for the amount of output voltage positioning required within the rated current range as discussed in the Adaptive Voltage Positioning section (Figure 4). R R +R L xV VOUT(NL) = 1 + IN x H REF RF RL (3) (Figures 1, 2). V REF = 0.6V (MAX5065) or 0.8V (MAX5067). Some applications require VOUT equal to VOUT(NOM) at no load. To ensure that the output voltage does not exceed the nominal output voltage (VOUT(NOM)), add a resistor RX from VCC to EAN. Use the following equations to calculate the value of RX. For MAX5065: RX = [VCC - 1.2] x For MAX5067: RX = [VCC - 1.4] x RF 0.8V (5) RF 0.6V (4)
MAX5065/MAX5067
Adaptive Voltage Positioning
Powering new-generation processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. A larger allowed, voltage-step excursion reduces the required number of output capacitors
where RH and RL are the feedback resistor network
DRV_VCC
PEAK-CURRENT COMPARATOR 112mV CLP_ CSP_ CSN_ GMIN RAMP 2 x fs (V/s) CLK R Q LX_ DL_ AV = 18 Gm = 500S PWM COMPARATOR S Q DH_
BST_
SHDN
PGND
Figure 5. Phase Circuit (Phase 1/Phase 2) ______________________________________________________________________________________ 19
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
VCNTR + VOUT/2
VCNTR
VCNTR - VOUT/2
NO LOAD
1/2 LOAD LOAD (A)
FULL LOAD
compensation provides a zero defined by 1 / [R4 x (C31 + C32)] and a pole defined by 1 / (R4 x C32). Use the following typical values for compensating the PLL: R4 = 7.5k, C31 = 4.7nF, C32 = 470pF. If changing the PLL frequency, expect a finite locking time of approximately 200s. The MAX5065/MAX5067 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL in order to generate the proper internal PWM clocks.
VOLTAGE-POSITIONING WINDOW
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive the gates of external N-channel MOSFETs (Figures 1, 2, and 3). The drivers' high-peak sink and source current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced cross-conduction losses. For modern CPU voltage-regulating module applications where the duty cycle is less than 50%, choose highside MOSFETs (Q1 and Q3) with a moderate RDS(ON) and a very low gate charge. Choose low-side MOSFETs (Q2 and Q4) with very low R DS(ON) and moderate gate charge. The driver block also includes a logic circuit that provides an adaptive nonoverlap time to prevent shoot-through currents during transition. The typical nonoverlap time is 60ns between the high-side and low-side MOSFETs.
Figure 6. Defining the Voltage-Positioning Window
or allows for the use of higher ESR capacitors. Voltage positioning may require the output to regulate away from a center value. Define the center value as the voltage where the output drops (VOUT/2) at one half the maximum output current (Figure 6). Set the voltage-positioning window (VOUT) using the resistive feedback of the VEA. Use the following equations to calculate the voltage-positioning window for the MAX5065/MAX5067: (6) I x RIN RH + RL VOUT = OUT x RL 2 x GC x RF (7) GC = 0.05 RS
BST_
The MAX5067 uses VDD to power the low- and highside MOSFET drivers. The high-side drivers derive their power through a bootstrap capacitor and VDD supplies power internally to the low-side drivers. Connect a 0.47F low-ESR ceramic capacitor between BST_ and LX_. Bypass VCC to SGND with 4.7F and 0.1F lowESR ceramic capacitors in parallel. Reduce the PC board area formed by these capacitors, the rectifier diodes between V CC and the boost capacitor, the MAX5065/MAX5067, and the switching MOSFETs.
where RIN and RF are the input and feedback resistors of the VEA, GC is the current-loop transconductance, and RS is the current-sense resistor.
Phase-Locked Loop: Operation and Compensation
The PLL synchronizes the internal oscillator to the external frequency source when driving CLKIN. Connecting CLKIN to VCC or SGND forces the PWM frequency to default to the internal oscillator frequency of 500kHz or 250kHz, respectively. The PLL uses a conventional architecture consisting of a phase detector and a charge pump capable of providing 20A of output current. Connect an external series combination capacitor (C31) and resistor (R4) and a parallel capacitor (C32) from PLLCMP to SGND to provide frequency compensation for the PLL (Figure 1). The pole-zero pair
Overload Conditions
Average-current-mode control has the ability to limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the VEA output clamps to +0.9V with respect to the common-mode voltage (VCM = +0.6V) and is compared with the output of the current-sense amplifiers (CA1 and CA2) (see Figure 4). The current-sense amplifier's gain of 18 limits the maximum current in the inductor or sense resistor to ILIMIT = 50mV/RS.
20
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Protection
The MAX5067 includes output overvoltage protection (OVP), undervoltage protection (UVP), phase failure, and overload protection to prevent damage to the powered electronic circuits.
Power-Good Generator (MAX5067)
The PGOOD output is high if all of the following conditions are met (Figure 8): 1) The output is within 90% to 108% of the programmed output voltage. 2) Both phases are providing current. 3) EN is high. A window comparator compares the differential amplifier output (DIFF) against 1.08 times the set output voltage for overvoltage and 0.90 times the set output voltage for undervoltage monitoring. The phase-failure comparator detects a phase failure by comparing the current-erroramplifier output (CLP_) with a 2.0V reference. Use a 10k pullup resistor from PGOOD to a voltage source less than or equal to VCC. An output voltage outside the comparator window or a phase-failure condition forces the open-drain output low. The open-drain MOSFET sinks 4mA of current while maintaining less than 0.2V at the PGOOD output.
MAX5065/MAX5067
Overvoltage Protection (MAX5067)
The OVP comparator compares the OVPIN input to the overvoltage threshold (Figure 7). The overvoltage threshold is typically +0.8V. A detected overvoltage event latches the comparator output forcing the power stage into the OVP state. In the OVP state, the highside MOSFETs turn off and the low-side MOSFETs latch on. Use the OVPOUT high-current output driver to turn on an external crowbar SCR. When the crowbar SCR turns on, a fuse must blow or the source current for the MAX5067 regulator must be limited to prevent further damage to the external circuitry. Connect the SCR close to the input source and after the fuse. Use an SCR large enough to handle the peak I2t energy due to the input and output capacitors discharging and the current sourced by the power-source output. Connect DIFF to OVPIN for differential output sensing and overvoltage protection. Add an RC delay to reduce the sensitivity of the overvoltage circuit and avoid nuisance tripping of the converter (Figures 1, 2). Connect a resistor-divider from the load to SGND to set the OVP output voltage. R VOVP = 1+ A x 0.8V RB (8)
DIFF 8% OF VREF VREF
PGOOD
RA OVPIN RB VOUT
10% OF VREF
MAX5067
DIFF
CLP1
+2.0V
RIN EAN RF EAOUT
CLP2 PHASE-FAILURE DETECTION
Figure 7. OVP Input Delay
Figure 8. Power-Good Generator (MAX5067) 21
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
SENSE+ SENSEVCC PHASE
CSN1 CSP1 VIN DH1 LX1 DL1
VCC CLKIN
MAX5065/ MAX5067 DH2 LX2
VIN
VIN
IN DIFF EAN
DL2
CSP2
CSN2 EAOUT PGND SGND CLKOUT
CLKIN
CSN1 CSP1 VIN DH1
VCC PHASE
LX1 DL1
IN
MAX5065/ MAX5067 DH2
VIN
DIFF
LX2 DL2
LOAD
VOUT = +0.6V (MAX5065) VOUT = +0.8V (MAX5067)
EAN EAOUT CSP2 CSN2 PGND SGND CLKOUT
CLKIN
CSN1 CSP1 VIN DH1
VCC PHASE
LX1 DL1
IN
MAX5065/ MAX5067 DH2
VIN
DIFF
LX2 DL2
EAN EAOUT CSP2 CSN2 PGND SGND CLKOUT
TO OTHER MAX5065/MAX5067s
Figure 9. Parallel Configuration of Multiple MAX5065/MAX5067s 22 ______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
VIN = +12V VIN VCC C31 C32 R13 2.2 C1, C2 2 x 47F
C43
R12 R4
C42 0.1F
VIN C3-C7 5 x 22F
OVPOUT
PLLCMP CLKIN
IN
SENSE- SENSE+ CSN1 CSP1 DH1 LX1 DL1 Q2 D1 D3 BST1 C12 0.47F Q1 L1 0.6H R1 1.35m
VCC EN
VCC R3 VDD OVPIN R7 DIFF EAN R8 EAOUT LX2 DL2 Q4 D2 DH2 Q3 MAX5067 (MASTER) VIN 4 x 22F C8-C11 C39 1F
C41 0.1F C40 1F
C38 4.7F
D4
L2 0.6H C13 0.47F
R2 1.35m
CLP1
CLP2
PGND
SGND
CLKOUT
PHASE PGOOD
CSN2 CSP2
BST2
R6 C36 C35
R5 C34 C33 VCC PGOOD
R11
C70 C71 R17
R24 2.2 VIN C46-C50 5 x 22F CLKIN SENSE- SENSE+ CSN1 CSP1 DH1 LX1 DL1 Q6 D5 D7 BST1 VCC R16 C64 0.1F C63 0.1F C65 4.7F C55 0.47F Q5 L3 0.6H R14 1.35m
C14, C15, C44, C45 2 x 100F C16-C25, C57-C60 2 x 270F
C26-C30, C37 6 x 10F LOAD
RH
RA
RL
RB VOUT = +0.8V TO +3.3V AT 104A
C61 0.1F EN PLLCMP IN
OVPOUT OVPIN MAX5067 (SLAVE)
VDD
C62 1F
D8
R20 VIN DIFF EAN R21 EAOUT LX2 DL2 Q8 D6 C56 0.47F DH2 Q7 L4 0.6H R15 1.35m C51-C54 4 x 22F
CLP1
CLP2
PGND
SGND
PHASE
PGOOD
CSN2 CSP2
BST2
R19 C66 C67
R18 C69 C68 VCC
Figure 10. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +0.8V to +3.3V at 104A) ______________________________________________________________________________________ 23
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Phase-Failure Detector (MAX5067)
Output current contributions from the two phases are within 10% of each other. Proper current sharing reduces the necessity to overcompensate the external components. However, an undetected failure of one phase driver causes the other phase driver to run continuously as it tries to provide the entire current requirement to the load. Eventually, the stressed operational phase driver fails. During normal operating conditions, the voltage level on CLP_ is within the peak-to-peak voltage levels of the PWM ramp. If one of the phases fails, the control loop raises the CLP_ voltage above its operating range. To determine a phase failure, the phase-failure detection circuit (Figure 8) monitors the output of the current amplifiers (CLP1 and CLP2) and compares them to a 2.0V reference. If the voltage levels on CLP1 or CLP2 are above the reference level for more than 1250 clock cycles, the phase failure circuit forces PGOOD low. tion, respectively. Figure 1 shows the typical application circuit for a two-phase operation. The design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching MOSFETs, sense resistors, and the compensation network. Follow the same procedure for the four- and sixphase converter design, except for the input and output capacitance. The input and output capacitance requirements vary depending on the operating duty cycle. The examples discussed in this data sheet pertain to a typical application with the following specifications: VIN = +12V VOUT = +1.8V IOUT(MAX) = 52A fSW = 250kHz Peak-to-Peak Inductor Current (IL) = 10A Table 1 shows a list of recommended external components (Figure 1) and Table 2 provides component supplier information.
Parallel Operation
For applications requiring large output current, parallel up to three MAX5065/MAX5067s (six phases) to triple the available output current (see Figures 9 and 10). The paralleled converters operate at the same switching frequency but different phases keep the capacitor ripple RMS currents to a minimum. Three parallel MAX5065/ MAX5067 converters deliver up to 180A of output current. To set the phase shift of the on-board PLL, leave PHASE unconnected for 90 of phase shift (2 paralleled converters), or connect PHASE to SGND for 60 of phase shift (3 converters in parallel). Designate one converter as master and the remaining converters as slaves. Connect the master and slave controllers in a daisychain configuration as shown in Figure 9. Connect CLKOUT from the master controller to CLKIN of the first slaved controller, and CLKOUT from the first slaved controller to CLKIN of the second slaved controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors. The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the DIFF voltage. Disable the voltage sensing of the slaved controllers by leaving DIFF unconnected (floating). Figure 10 shows a detailed typical parallel application circuit using two MAX5067s. This circuit provides four phases at an input voltage of +12V and an output voltage range of +0.6V to +3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) at 104A.
Number of Phases
Selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty cycle and the number of phases. Use the following equation as a starting point to choose the number of phases: NPH K/D (9) where K = 1, 2, or 3 and the duty cycle is D = VOUT/VIN. Choose K to make NPH an integer number. For example, converting V IN = +12V to V OUT = +1.8V yields better ripple cancellation in the six-phase converter than in the four-phase converter. Ensure that the output load justifies the greater number of components for multiphase conversion. Generally limiting the maximum output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation occurs when NPH = K/D. Single-phase conversion requires greater size and power dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, thereby reducing the input/output capacitance requirement for the same ripple performance. The lower inductance value improves the large-signal response of the converter during a transient load at the output. Consider
Applications Information
Each MAX5065/MAX5067 circuit drives two 180 out-ofphase channels. Parallel two or three MAX5065/ MAX5067 circuits to achieve four- or six-phase opera24
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Table 1. Component List
DESIGNATION C1, C2 C3-C11 C12, C13 C14, C15 C16-C25 C26-C30, C37 C31 C32, C34, C36 C33, C35, C43 C38 C39 C40, C41, C42 C44 D1, D2 D3, D4 L1, L2 Q1, Q3 Q2, Q4 R1, R2 R3, R13 R4 R5, R6 RIN Rf R11 R12 RA RB RH RL RX QTY 2 9 2 2 10 6 1 3 3 1 1 3 1 2 2 2 2 2 4 2 2 2 1 1 1 1 1 1 1 1 1 DESCRIPTION 47F,16V X5R input-filter capacitors TDK C5750X5R1C476M 22F, 16V input-filter capacitors TDK C4532X5R1C226M 0.47F, 16V capacitors TDK C1608X5R1A474K 100F, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3 270F, 2V output-filter capacitors Panasonic EEFUE0D271R 10F, 6.3V output-filter capacitors TDK C2012X5R05106M 4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ 470pF, 16V capacitors Murata GRM1885C1H471JAB01 0.01F, 50V X7R capacitors Murata GRM188R71H103KA01 4.7F, 16V X5R capacitor Murata GRM40-034X5R475k6.3 0.1F, 10V Y5V capacitor Murata GRM188F51A105 0.1F, 16V X7R capacitors Murata GRM188R71C104KA01 100pF--OVPIN capacitor Schottky diodes ON-Semiconductor MBRS340T3 Schottky diodes ON-Semiconductor MBR0520LT1 0.6H, 27A inductors Panasonic ETQP1H0R6BFX Upper-power MOSFETs Vishay-Siliconix Si7860DP Lower-power MOSFETs Vishay-Siliconix Si7886DP Current-sense resistors, use two 2.7m resistors in parallel, Panasonic ERJM1WSF2M7U 2.2 1% resistors 7.5k 1% resistor 1k 1% resistors 4.99k 1% resistor 37.4k 1% resistor 10k 1% resistor 10k 1% resistor See the Overvoltage Protection (MAX5067) section See the Overvoltage Protection (MAX5067) section See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections Open circuit
Table 2. Component Suppliers
SUPPLIER Murata ON Semiconductor Panasonic TDK Vishay-Siliconix PHONE 770-436-1300 602-244-6600 714-373-7939 847-803-6100 1-800-551-6933 FAX 770-436-3030 602-244-3345 714-373-7183 847-390-4405 619-474-8920 WEBSITE www.murata.com www.on-semi.com www.panasonic.com www.tcs.tdk.com www.vishay.com
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25
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
all these issues when determining the number of phases necessary for the voltage regulator application.
Inductor Selection
The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the output determine the inductance value. Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs create switching losses. The situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. Use 500kHz per phase for VIN = +5V and 250kHz or less per phase for VIN > +12V. Although lower switching frequencies per phase increase the peak-to-peak inductor ripple current (IL), the ripple cancellation in the multiphase topology reduces the input and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value:
MAX5065/MAX5067 limits the maximum peak inductor current and prevents the inductor from saturating. Choose an inductor with a saturating current greater than the worst-case peak inductor current. Use the following equation to determine the worst-case inductor current for each phase: 0.051V IL + 2 RSENSE
IL _ PEAK =
(12)
where RSENSE is the sense resistor in each phase.
Switching MOSFETs
When choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation, and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5065/ MAX5067 output is proportional to the total capacitance it drives from DH1, DH2, DL1, and DL2. The power dissipated in the MAX5065/MAX5067 is proportional to the input voltage and the average drive current. See the VIN, VCC, VDD section to determine the maximum total gate charge allowed from all the driver outputs combined. The gate charge and drain capacitance (CV2) loss, the cross-conduction loss in the upper MOSFET due to finite rise/fall time, and the I2R loss due to RMS current in the MOSFET RDS(ON) account for the total losses in the MOSFET. Estimate the power loss (PDMOS_) in the high-side and low-side MOSFETs using the following equations:
PDMOS - HI = (QG x VDD x fSW ) +
LMIN =
(VINMAX - VOUT ) x VOUT
VIN x fSW x IL
(10)
Choose IL equal to about 40% of the output current per phase. Since IL affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material for custom inductors. High IL causes large peak-to-peak flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with high IL, reduces the required minimum inductance and even makes the use of planar inductors possible. The advantages of using planar magnetics include lowprofile design, excellent current-sharing between phases due to the tight control of parasitics, and low cost. For example, calculate the minimum inductance at VIN(MAX) = +13.2V, VOUT = +1.8V, IL = 10A, and fSW = 250kHz:
(13)
VIN x IOUT x ( t R + t F ) x fSW 2 + 1.4RDS(ON) x I RMS - HI 4
where QG, RDS(ON), tR, and tF are the upper-switching MOSFET's total gate charge, on-resistance at +25C, rise time, and fall time, respectively.
LMIN
(13.2 - 1.8) x 1.8 = 0.6H =
13.2 x 250k x 10
(11)
IRMS-HI =
(I
D 2 2 DC + I PK + IDC x IPK x 3
)
(14)
The average-current-mode control feature of the
26
where D = V OUT /V IN , I DC = (I OUT - I L )/2 and I PK = (IOUT + IL)/2
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Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
PDMOS - LO = (QG x VDD x fSW ) +
Input Capacitors
The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. Increasing the number of phases increases the effective switching frequency and lowers the peak-to-average current ratio, yielding a lower input capacitance requirement. The input ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high-ripple-current capability at the input. Assume the contributions from the ESR and capacitor discharge are equal to 30% and 70%, respectively. Calculate the input capacitance and ESR required for a specified ripple using the following equation: ESRIN =
MAX5065/MAX5067
(15) 2 2xC 2 OSS x VIN x fSW + 1.4R DS(ON) x I RMS - LO 3
where COSS is the MOSFET drain-to-source capacitance.
IRMS-LO =
(I
1- D 2 2 DC + I PK + IDC x IPK x 3
)
(
)
(16)
For example, from the typical specifications in the Applications Information section with VOUT = +1.8V, the high-side and low-side MOSFET RMS currents are 9.9A and 24.1A, respectively. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least 25C below the absolute maximum rating. Use the following equation to calculate maximum junction temperature: TJ = PDMOS x J-A + TA (17)
IOUT IL + N 2
(VESR )
(18)
Table 3. Peak-to-Peak Output Ripple Current Calculations
NUMBER OF PHASES (N) 2 DUTY CYCLE (D) < 50% EQUATION FOR IP-P
IOUT x D(1 - D) CIN = N VQ x fSW
(19)
where IOUT is the total output current of the multiphase converter and N is the number of phases. For example, at V OUT = +1.8V, the ESR and input capacitance are calculated for the input peak-to-peak ripple of 100mV or less yielding an ESR and capacitance value of 1m and 200F.
V (1 - 2D) I = O L x fSW I =
2
> 50%
(VIN - VO )(2D - 1)
L x fSW
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. In multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. The degree of ripple cancellation depends on the operating duty cycle and the number of phases. Choose the right equation from Table 3 to calculate the peak-to-peak output ripple (IP-P) for a given duty cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH = K / D.
4
0 to 25%
V (1- 4D) I = O L x fSW V (1 - 2D)(4D - 1) I = O 2 x D x L x fSW V (2D - 1)(3 - 4D) I = O D x L x fSW V (1- 6D) I = O L x fSW
4
25% to 50%
4
> 50%
6
< 17%
______________________________________________________________________________________
27
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
The allowable deviation of the output voltage during the fast transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge causes a voltage drop during a step load. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window (VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the following equations to calculate the required ESR and capacitance value: ESROUT = VESR ISTEP (20) Calculate the maximum reverse current based on VCLR, the reverse-current-limit threshold, and the current-sense resistor. IREVERSE = 2 x VCLR RSENSE (24)
where IREVERSE is the total reverse current into the converter.
Compensation
The main control loop consists of an inner current loop and an outer voltage loop. The MAX5065/MAX5067 use an average-current-mode control scheme to regulate the output voltage (Figure 4). IPHASE1 and IPHASE2 are the inner average current loops. The VEA output provides the controlling voltage for these current sources. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. A resistive feedback around the VEA provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions, RF and RIN determine the VEA gain. Use the following equation to calculate the value for RF: RF = IOUT x RIN N x GC x VOUT GC = 0.05 RS (25)
I xt COUT = STEP RESPONSE VQ
(21)
where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth.
Current Limit
The average-current-mode control technique of the MAX5065/MAX5067 accurately limits the maximum output current per phase. The MAX5065/MAX5067 sense the voltage across the sense resistor and limit the peak inductor current (IL-PK) accordingly. The ON cycle terminates when the current-sense voltage reaches 45mV (min). Use the following equation to calculate maximum current-sense resistor value: RSENSE = 0.045 IOUT N (22)
(26)
PDR =
2.5 x 10-3 RSENSE
(23)
where GC is the current-loop transconductance and N is number of phases. When designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the CEA output) does not exceed the ramp slope. This is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to calculate the resistor RCF: RCF 2 x fSW x L x 102 VOUT x RSENSE (27)
where PDR is the power dissipation in sense resistors. Select 5% lower value of RSENSE to compensate for any parasitics associated with the PC board. Also, select a non inductive resistor with the appropriate wattage rating.
Reverse Current Limit
The MAX5065/MAX5067 limit the reverse current when VBUS is higher than the preset output voltage.
For example, the maximum RCF is 12k for RSENSE = 1.35m. CCF provides a low-frequency pole while RCF provides a midband zero. Place a zero at fZ to obtain a phase bump at the crossover frequency. Place a high-frequency pole
28
______________________________________________________________________________________
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
(fP) at least a decade away from the crossover frequency to achieve maximum phase margin. Use the following equations to calculate CCF and CCFF: CCF = 1 2 x x fZ x RCF (28) 7) Avoid long traces between the VCC bypass capacitors, driver output of the MAX5065/MAX5067, MOSFET gates and PGND pin. Minimize the loop formed by the VCC bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5065/MAX5067, and upper MOSFET gate. 8) Place the bank of output capacitors close to the load. 9) Distribute the power components evenly across the board for proper heat dissipation. 10) Provide enough copper area at and around the switching MOSFETs, inductor, and sense resistors to aid in thermal dissipation. 11) Use at least 4oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
MAX5065/MAX5067
1 CCFF = 2 x x fP x RCF
(29)
PC Board Layout
Use the following guidelines to layout the switching voltage regulator: 1) Place the VIN and VCC bypass capacitors close to the MAX5065/MAX5067. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop from the lower-switching MOSFET, inductor, and output capacitor. 4) Place the Schottky diodes close to the lower MOSFETs and on the same side of the PC board. 5) Keep the SGND and PGND isolated and connect them at one single point close to the negative terminal of the input-filter capacitor. 6) Run the current-sense lines CS+ and CS- very close to each other to minimize the loop area. Similarly, run the remote-voltage sense lines SENSE+ and SENSE- close to each other. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of the current-sense resistors.
Chip Information
TRANSISTOR COUNT: 5451 PROCESS: BiCMOS
Selector Guide
PART MAX5065 MAX5067 OUTPUT Adjustable +0.6V to +3.3V Adjustable +0.8V to +3.3V with OVP, PGOOD, Phase Failure Detector
______________________________________________________________________________________
29
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Pin Configurations
PLLCMP PHASE CLKOUT CLKIN CSN2 CSP2 CLP2 SGND BST2
TOP VIEW
CSP2 1 CSN2 2 PHASE 3 PLLCMP 4 CLP2 5 SGND 6 CLP1 7 SENSE+ 8 SENSE- 9 DIFF 10 EAN 11 EAOUT 12 CSP1 13 CSN1 14 28 CLKIN 27 CLKOUT 26 BST2 25 DH2 24 LX2 N.C. N.C. N.C. N.C. SGND 23 DL2 22 PGND 21 IN 20 VCC 19 DL1 18 LX1 17 DH1 16 BST1 15 EN OVPIN CLP1 OVPOUT PGOOD SENSE+ SENSE1 2 3 4 5 6 7 8 9 10 11
N.C.
44 43 42 41 40 39 38 37 36 35 34 33 32 31 N.C. DH2 LX2 DL2 PGND IN VCC VDD DL1 LX1 DH1*
N.C.
MAX5067
30 29 28 27 26 25 24 23
MAX5065
12 13 14 15 16 17 18 19 20 21 22
EN
N.C.
SGND
CSN1
DIFF
N.C.
EAN
EAOUT
28 SSOP
44 THIN QFN*
*CONNECT THE THIN QFN EXPOSED PAD TO SGND GROUND PLANE.
30
_____________________________________________________________________________________
CSP1
BST1
N.C.
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
SSOP.EPS
MAX5065/MAX5067
2
1
INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015
MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L
0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC
N
A C B e D A1 L
NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL DOCUMENT CONTROL NO. REV.
21-0056
1 1
C
______________________________________________________________________________________
31
Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32, 44, 48L QFN.EPS
E2/2
C L
D2 D D/2 k
C L
b D2/2
E/2
E
(NE-1) X e
E2
k L DETAIL A e (ND-1) X e
C L
C L
L
L
e
e
A1
A2
A
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
1 2
C
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
2 2
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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